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AD7322
Preliminary Technical Data
TIMING SPECIFICATIONS
Table 2. Unless otherwise noted,
V
DD
= +4.75V to + 16.5V, V
SS
= -4.75 to –16.5V, V
CC
=2.7V to 5.25, V
DRIVE
=2.7V to 5.25, V
REF
=
2.5V Internal/External, T
A
= T
MAX
to T
MIN
Parameter
Limit at T
MIN
, T
MAX
Unit
Description
f
SCLK
10
kHz min
20
MHz max
t
CONVERT
16×t
SCLK
ns max
T
SCLK
= 1/f
SCLK
t
QUIET
50
ns max
Minimum Time between End of Serial Read and Next Falling Edge of CS
t
1
10
ns min
Minimum CS Pulse width
t
2
10
ns min
CS to SCLK Setup Time
t
3
20
ns max
Delay from CS until D
OUT
Three-State Disabled
t
4
TBD
ns max
Data Access Time after SCLK Falling Edge.
t
5
0.4t
SCLK
ns min
SCLK Low Pulsewidth
t
6
0.4t
SCLK
ns min
SCLK High Pulsewidth
t
7
10
ns min
SCLK to Data Valid Hold Time
t
8
25
ns max
SCLK Falling Edge to D
OUT
High Impedance
10
ns min
SCLK Falling Edge to D
OUT
High Impedance
t
9
TBD
ns min
DIN set-up time prior to SCLK falling edge
t
10
5
ns min
DIN hold time after SCLK falling edge
1
μs max
Power up from Auto Standby
TBD
μs max
Power up from Full Shutdown/Auto Shutdown Mode
Figure 2. Serial Interface timing Diagram
Rev. PrE | Page 5 of 18
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